Structure and method for forming asymmetrical overlap capacitance in field effect transistors

ABSTRACT

A method for forming asymmetric spacer structures for a semiconductor device includes forming a spacer layer over at least a pair of adjacently spaced gate structures disposed over a semiconductor substrate. The gate structures are spaced such that the spacer layer is formed at a first thickness in a region between the gate structures and at a second thickness elsewhere, the second thickness being greater than said first thickness. The spacer layer is etched so as to form asymmetric spacer structures for the pair of adjacently spaced gate structures.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a division of U.S. patent application Ser. No.11/163,165, filed Oct. 7, 2005, the disclosure of which is incorporatedby reference herein in its entirety.

TRADEMARKS

IBM® is a registered trademark of International Business MachinesCorporation, Armonk, N.Y., U.S.A. Other names used herein may beregistered trademarks, trademarks or product names of InternationalBusiness Machines Corporation or other companies.

BACKGROUND

The present invention relates generally to semiconductor deviceprocessing techniques, and, more particularly, to a structure and methodfor forming asymmetrical overlap capacitance in field effect transistors(FETs).

In the manufacture of semiconductor devices, there is a constant driveto increase the operating speed of certain integrated circuit devicessuch as microprocessors, memory devices, and the like. This drive isfueled by consumer demand for computers and other electronic devicesthat operate at increasingly greater speeds. As a result of the demandfor increased speed, there has been a continual reduction in the size ofsemiconductor devices, such as transistors. For example, in a devicesuch as a field effect transistor (FET), device parameters such aschannel length, junction depth and gate dielectric thickness, to name afew, all continue to be scaled downward.

Generally speaking, the smaller the channel length of the FET, thefaster the transistor will operate. Moreover, by reducing the sizeand/or scale of the components of a typical transistor, there is also anincrease in the density and number of the transistors that may beproduced on a given amount of wafer real estate, thus lowering theoverall cost per transistor as well as the cost of integrated circuitdevices incorporating such transistors.

Unfortunately, reducing the channel length of a transistor alsoincreases “short channel” effects, as well as “edge effects” that arerelatively unimportant in long channel transistors. One example of ashort channel effect includes, among other aspects, an increased drainto source leakage current when the transistor is supposed to be in the“off” or non-conductive state, due to an enlarged depletion regionrelative to the shorter channel length. In addition, one of the edgeeffects that may also adversely influence transistor performance is whatis known as Miller capacitance. The Miller capacitance is a parasiticoverlap capacitance (C_(ov)) that arises as a result of the dopedpolycrystalline silicon gate electrode and gate dielectric that (almostinvariably) overlaps with a conductive portion of the more heavily dopedsource/drain regions and/or the less heavily doped source/drainextension (SDE) regions (if present) of the FET.

Moreover, as transistor dimensions continue to scale down, the gate tosource/drain extension overlap needs to be kept relatively constant sothat drive current can be maintained. For example, a minimum of about 20nm/side of overlap is necessary to prevent transistor drive current(I_(dsat)) degradation. When an overlap is too small, a high resistanceregion will be created between the extension and the channel. As devicesbecome smaller, the source extension to drain extension distance becomesnarrower, resulting in a severe punchthrough problem.

Accordingly, it would be desirable to be able to fabricate an FET devicethat maintains a low series resistance between the gate and the sourceof the device, while at the same time minimizing adverse consequencessuch as short channel effects, hot carrier effects, punchthrough andparasitic Miller capacitance formed by excessive gate to drain overlap.

SUMMARY

The foregoing discussed drawbacks and deficiencies of the prior art areovercome or alleviated by a method for forming asymmetric spacerstructures for a semiconductor device. In an exemplary embodiment, themethod includes forming a spacer layer over at least a pair ofadjacently spaced gate structures disposed over a semiconductorsubstrate. The gate structures are spaced such that the spacer layer isformed at a first thickness in a region between the gate structures andat a second thickness elsewhere, the second thickness being greater thansaid first thickness. The spacer layer is etched so as to formasymmetric spacer structures for the pair of adjacently spaced gatestructures.

In another embodiment, a method for forming field effect transistor(FET) structures for a semiconductor device includes forming at least apair of adjacently spaced gate structures over a semiconductorsubstrate, and forming a spacer layer over the adjacently spaced gatestructures. The gate structures are spaced such that the spacer layer isformed at first thickness in a region between the gate structures and ata second thickness elsewhere, the said second thickness being greaterthan said first thickness. The spacer layer is etched so as to formasymmetric spacer structures adjacent sidewalls of the pair ofadjacently spaced gate structures, and the substrate is implanted withdoped regions having asymmetric characteristics in accordance with theasymmetric spacer structures.

In still another embodiment, a method for forming field effecttransistor (FET) structures for a semiconductor device includes formingat least a pair of adjacently spaced gate structures over asemiconductor substrate, forming offset spacers adjacent sidewalls ofthe pair of adjacently spaced gate structures, and forming extensionregions in the substrate. A second spacer layer is formed over theoffset spacers, the gate structures and the substrate. The second spacerlayer is subjected to a single, angled ion implantation of a neutralspecies, the angled ion implantation originating from a singledirection. The second spacer layer is etched, wherein portions of thesecond spacer layer subjected to said angled ion implantation are etchedat a faster rate than unexposed portions thereof, thereby formingasymmetrical second spacers adjacent the offset spacers. The substrateis then implanted with source and drain regions.

In still another embodiment, a field effect transistor (FET) device,includes a gate structure formed over a semiconductor substrate, a firstpair of spacer structures formed on sidewalls of the gate structure, anda second pair of spacer structures formed adjacent the first pair ofspacer structures, the second pair of spacer structures having anasymmetrical thickness with respect to one another. A source region andextension thereof is implanted on one side of the gate structure, and adrain region and extension thereof is implanted on the other side of thegate structure. The extension of the source region has a differentlength than the extension of the drain region, in accordance with saidasymmetrical thickness of the second pair of spacer structures.

BRIEF DESCRIPTION OF THE DRAWINGS

Referring to the exemplary drawings wherein like elements are numberedalike in the several Figures:

FIGS. 1 through 3 are a series of a cross sectional views illustratingthe formation of asymmetrical source and drain overlap regions in an FETdevice, in accordance with an exemplary embodiment of the invention;

FIGS. 4 through 7 and FIG. 9 are a series of a cross sectional viewsillustrating the formation of asymmetrical source and drain extensionregions in an FET device, in accordance with an alternative embodimentof the invention;

FIG. 8 is an exemplary SEM image of a device formed in accordance withthe processing step shown in FIG. 7;

FIG. 10 is an exemplary SEM image of a portion of an SRAM cell havingasymmetric spacers;

FIGS. 11 through 14 are a series of a cross sectional views illustratingthe formation of asymmetrical source and drain overlap regions in an FETdevice, in accordance with an alternative embodiment of the invention;and

FIGS. 15 through 20 are a series of a cross sectional views illustratingthe formation of asymmetrical source and drain extension regions in anFET device, in accordance with still another embodiment of theinvention.

DETAILED DESCRIPTION

Disclosed herein is a method and structure for reducing overlapcapacitance in field effect transistors (FETs). In a conventional FETfabrication process, the spacer structures formed on opposite sides ofthe gate conductor are generally symmetrical, such that subsequentlyformed source and drain extensions have the same amount of overlap withrespect to the gate. However, because the transistor drive current isprimarily controlled by the amount of source side overlap (i.e., gate tosource resistance), the amount of drain side overlap can still bereduced without adversely impacting drive current. On the other hand,the reduction in gate to drain overlap is beneficial in terms of shortchannel effects, punchthrough, hot carrier effects and parasiticcapacitance, for example.

Furthermore, as device dimensions shrink, the extension resistancebecomes dominant. A shorter source side extension (as a result of anarrow spacer width) will reduce the series resistance and improvedevice performance, without also causing problems such as hot carriereffects, since the drain side extension (as a result of not reducing thespacer width) is still maintained at an appropriate length. This is incontrast to conventionally formed symmetrical extensions for the sourceand drain sides, which in turn result in symmetrical source and drainextension lengths.

Accordingly, as described in further detail herein, the disclosedinvention embodiments utilize various fabrication techniques to produceasymmetric spacer structures that in turn result in source and drainextension having long and short overlaps, as well as long and shortextensions themselves.

Referring initially to FIGS. 1 through 3, there is shown a series of across sectional views illustrating the formation of asymmetrical sourceand drain overlap regions for a pair of FET devices 100, in accordancewith an exemplary embodiment of the invention. In particular, FIG. 1illustrates a pair of adjacent gate conductors 102 formed over asemiconductor substrate 104 (e.g., silicon), with the gates 102 beingformed on corresponding gate oxide layers 106. Shallow trench isolation(STI) structures 108 are also illustrated for electrically isolatingindividual devices from one another on the substrate 104. As the basicFET structures are well known to one skilled in the art, certainfeatures such as the STIs 108 and gate oxide layers 106 are notdiscussed in further detail herein.

As is also shown in FIG. 1, a spacer layer 130 of non-uniform thicknessis formed over a pair of gate structures 102. The embodiment of FIG. 1makes use of two neighboring gates in close proximity (e.g., aseparation therebetween of about 1 to 3 times the gate height). Byselectively tuning the deposition parameters in forming the spacer layer130, a thinner film will be formed over the region between the two gateswith respect to the regions on the outside of the gates. As such, whenthe spacer layer 130 is patterned and etched, the asymmetric spacers 114a, 114 b will result from the constant etch rate of a layer ofnon-uniform thickness, as illustrated in FIG. 2.

Following the formation of the asymmetrical spacers, FIG. 3 illustratesa halo and extension implantation step in accordance with standarddevice processing. After an anneal to drive the implanted dopantmaterials, it is seen that the extensions 116 corresponding to thethinner spacers 114 b have longer overlaps than the extensions 118corresponding to the thicker spacers 114 a. In other words, the “longoverlap” extensions 116 extend further beneath the gate than do the“short overlap” extensions 118. In a preferred embodiment, the sourceterminal of the FET structures will be located at the long overlapextension side of the gate (to maintain drive current) while the drainterminal is located at the short overlap extension side of the gate (toreduce overall overlap capacitance and improve short channel effects).

The principles of asymmetric spacer formation through non-uniform layerformation may also be applied during the formation of the deep sourceand drain regions as well. FIGS. 4 through 7 and FIG. 9 are a series ofa cross sectional views illustrating the formation of asymmetricalsource and drain extension regions in an FET device, in accordance withanother embodiment of the invention. Beginning in FIG. 4, offset spacers114 are initially formed over the FET gate structures.

The spacers 114 may be symmetrical (i.e., substantially equal thicknesson both sides of the gate) as in a conventional process or,alternatively, the spacers 114 could be formed asymmetrically as shownin FIG. 2. For purposes of illustration, the offset spacers 114 aredepicted as symmetric in the present sequence. FIG. 5 illustrates a haloand extension implantation step in accordance with standard deviceprocessing, followed by an anneal to diffuse the implanted dopantmaterials. For symmetrical offset spacers 114, the resulting extensions120 on both sides of the gates will have substantially equal overlaps.On the other hand, if the spacers 114 are formed in accordance with theprocessing shown in FIGS. 1-2, then asymmetrical extensions will appearas shown in FIG. 3.

As then shown in FIG. 6, a non-uniform second spacer layer 132 (e.g.,Si₃N₄) is formed over the device. Similar to the embodiment of FIG. 1,the second spacer layer 132 (given a sufficiently close distance betweengates and properly tuned process conditions) will be formed thinner inthe region between the gates, and thicker in the regions outside thegates. Once the second spacer layer 132 is patterned and etched in FIG.7, the asymmetric spacers 124 a, 124 b are formed. By way ofillustration, FIG. 8 is an exemplary SEM image of a device formed inaccordance with the processing step shown in FIG. 7.

Through the formation of the asymmetric spacers 124 a, 124 b, thesource/drain ion implantation step shown in FIG. 9 results in extensionswith different lengths. More specifically, the extensions 120 a on theoutside of the gates are longer in comparison to the extensions 120 bbetween the gates. This is due to the fact that the deep source/drainimplant comes closer to the gate where the second set of spacers isthinner, thus shortening the extension regions formed in FIG. 5. Withsuch shorter extensions, there is a lower resistance to carriers (e.g.,electrons or holes). In such an embodiment, it would be practical tohave a common source terminal located between the gates to reduce theseries resistance, while the drain terminals are located outside thegates where the extensions are longer.

One suitable example of such an application could be the PFET devicepair of an SRAM cell, which has the source terminals thereof connectedto the supply voltage (V_(DD)). FIG. 10 is an exemplary SEM image of aportion of an SRAM cell having asymmetric spacers, similar to theembodiment shown in FIG. 9. As will be noted, the thinner spacers arelocated between the two gates.

FIGS. 11 through 14 illustrate another technique for forming asymmetricspacers, in accordance with a further embodiment of the invention. Aswith the previous embodiments discussed above, FIG. 11 illustrates apair of gate conductors 102 formed over a semiconductor substrate 104,gate oxide layers 106 and STI structures 108. In addition, a spacerlayer 110 (e.g., oxide, TEOS, silicon nitride) is formed over thedevices 100 for the purpose of forming spacers prior to dopantimplantation.

Conventionally, the spacer layer 110 of FIG. 11 would then be patternedand uniformly etched to result in substantially symmetric spacers alongthe sidewalls of the gate conductors 102. However, as shown in FIG. 12,the wafer is then subjected to an angled ion implantation (arrows 112)of a neutral dopant species such as germanium (Ge) or xenon (Xe), forexample. This results in the spacer layer 110, on one side of the gatestructures, having receiving the angled ion implant. In an exemplaryembodiment, the implant angle may be on the order from about 10 degreesto about 35 degrees. The effect of such an implant is to increase theetch rate of implanted portions of the spacer layer 110 with respect tothe remainder of the layer. Thus, when the implanted spacer layer 110 issubsequently patterned and etched, as shown in FIG. 13, each gate isleft with a pair of spacers 114 a, 114 b, wherein the spacers 114 b onthe implanted side of the gate are thinner (i.e., asymmetrical) withrespect to the spacers 114 a on the non-implanted side of the gate.

Following the formation of the asymmetrical spacers, FIG. 14 illustratesa halo and extension implantation step to form the extensions havinglonger and shorter overlaps 116, 118, similar to the structure of FIG.3. However, whereas the longer overlaps 116 of FIG. 3 are located on theinside of the gates, the longer overlaps 116 of FIG. 14 are located onthe right side of the gates.

The principles of asymmetric spacer formation through ion implantationmay also be applied during the formation of the source and drain regionsas well. FIGS. 15 through 20 are a series of a cross sectional viewsillustrating the formation of asymmetrical source and drain extensionregions in an FET device, in accordance with another embodiment of theinvention. Beginning in FIG. 15, the FET structures are shown after theformation of offset spacers 114. As with FIG. 4, the offset spacers 114may either by symmetrically formed or asymmetrically formed prior to thehalo/extension ion implant step of FIG. 5.

FIG. 16 illustrates a halo and extension implantation step in accordancewith standard device processing, followed by an anneal to diffuse theimplanted dopant materials. For symmetrical offset spacers, theresulting extensions 120 on both sides of the gates will havesubstantially equal overlaps. On the other hand, if the spacers 114 areformed in accordance with the processing shown in FIGS. 12-13, then theextensions 120 will appear as shown in FIG. 14. In either case, a secondspacer layer 122 (e.g., Si₃N₄) is then formed over the device as shownin FIG. 17.

Then, as shown in FIG. 18, the second spacer layer 122 is subjected toan angled ion implantation (arrows 112) of a neutral dopant species, ina manner similar to that discussed in the previous embodiment. Again,this has the effect of increasing the etch rate of the implantedportions of the layer 122. Thus, when the layer 122 is patterned andetched as shown in FIG. 19, a second set of spacers 124 a, 124 b isformed over the first set of offset spacers 114. Regardless of whetherthe first set of offset spacers 114 is symmetric or asymmetric, thesecond set of spacers will in fact be asymmetric due to the angledimplantation shown in FIG. 18. In particular, the non-implanted side ofthe gate structures include thicker spacers 124 a, while the implantedside of the gate structure includes thinner spacers 124 b.

As finally illustrated in FIG. 20, the wafer is then subjected to a(deep) source/drain implantation in accordance with conventional processdoping. However, on the side of the gates corresponding to the thinnerspacers 124 b, the resulting extensions 120 b that remain after the deepsource/drain implant become shorter in length than the extensions 120 aon the side of the gates corresponding to the thicker spacers 124 a.Thus, in a preferred embodiment, the source side of the FETs is locatedat the sides of the gate corresponding to the thinner spacers 124 b. Incontrast, the drain side extensions are still maintained at a certainlength in order to prevent hot carrier effects.

Through the use of an angled, neutral dopant implantation step in orderto increase the etch rate of a spacer layer, an FET device havingasymmetrical spacer thicknesses may be achieved. This in turn allows forextensions with long/short overlaps, as well as longer and shorterextensions themselves. However, additional methods are also contemplatedthat will result in the asymmetric spacers such as discussed above.

While the invention has been described with reference to a preferredembodiment or embodiments, it will be understood by those skilled in theart that various changes may be made and equivalents may be substitutedfor elements thereof without departing from the scope of the invention.In addition, many modifications may be made to adapt a particularsituation or material to the teachings of the invention withoutdeparting from the essential scope thereof. Therefore, it is intendedthat the invention not be limited to the particular embodiment disclosedas the best mode contemplated for carrying out this invention, but thatthe invention will include all embodiments falling within the scope ofthe appended claims.

1. A semiconductor device, comprising: at least a pair of field effecttransistor (FET) structures including a pair of adjacently spaced gatestructures formed over a semiconductor substrate; each of said pair ofFET structures having a pair of asymmetric spacer structures adjacentsidewalls thereof; wherein inner spacer structures located in a regionbetween said pair of gate structures are thinner than outer spacerstructures located on the outside of said pair of gate structures. 2.The device of claim 1, wherein said asymmetric spacer structures furthercomprise offset spacers used in the definition of halo and extensionimplantation regions.
 3. The device of claim 1, further comprisingextensions implanted within said substrate, wherein said extensionscorresponding to thinner offset spacers have a longer gate overlap thansaid extensions corresponding to thicker offset spacers.
 4. The deviceof claim 1, wherein said asymmetric spacer structures further comprisesecond spacers formed over offset spacers, used in the definition ofsource and drain regions.
 5. The device of claim 4, further comprisingsource and drain regions implanted within said substrate, wherein saidsource regions correspond to thinner second spacers and said drainregions correspond to thicker second spacers.
 6. The device of claim 5,wherein said source regions have shorter extensions than said drainregions.
 7. The device of claim 1, wherein a distance between said pairof adjacently spaced gate structures is about 1 to 3 times a height ofsaid gate structures.
 8. A field effect transistor (FET) device,comprising: a gate structure formed over a semiconductor substrate; afirst pair of spacer structures formed on sidewalls of said gatestructure; a second pair of spacer structures formed adjacent said firstpair of spacer structures, said second pair of spacer structures havingan asymmetrical thickness with respect to one another; a source regionand extension thereof implanted on one side of said gate structure; anda drain region and extension thereof implanted on the other side of saidgate structure; wherein the extension of said source region has adifferent length than the extension of said drain region, in accordancewith said asymmetrical thickness of said second pair of spacerstructures.
 9. The FET device of claim 8, wherein said source regioncorresponds to a thinner one of said second pair of spacer structuresand said drain regions corresponds to a thicker one of said second pairof spacer structures.
 10. The FET device of claim 9, wherein theextension of said source region is shorter than the extension of saiddrain region.
 11. The FET device of claim 8, wherein said first pair ofspacer structures also have an asymmetrical thickness with respect toone another.
 12. The FET device of claim 11, wherein one of said sourceand drain extensions corresponding to a thinner one of said first pairof spacer structures has a longer gate overlap than the other of saidsource and drain extensions corresponding to a thicker one of said firstpair of spacer structures.
 13. The FET device of claim 12, wherein theextension of said source region has a longer gate overlap than theextension of said drain region.